1. Technical Field
The present invention relates in general to the field of computers, and in particular to the simulation of electronic Devices Under Test (DUT). Still more particularly, the present invention describes a graphical method of generating test sequences based on current simulation results.
2. Description of the Related Art
The product development of a System On a Chip (SOC) encompasses various levels of verification that include functional, behavioral and formally parameterized testing. Several techniques and methods are used to determine the completeness of the verification effort. One common method is to generate a comprehensive list of complex stimulus sequences that represent the various scenarios needed to validate the Design Under Test (DUT), which is a combination of the SOC hardware and a software wrapper associated with the SOC. As the complexity of the DUT grows, so does the complexity of the needed scenarios.
The traditional method of generating these complex scenarios is through manual coding, or parameterized stimulus generators. The required time to produce such design verification code can be very long, the task tedious, and error prone. In addition, there are such scenarios called corner cases, which are defined as very specific although very unusual complex DUT operating scenarios that have the property of being difficult to predict. It is difficult, if not impossible, to code in a directed test case that represents a corner case.
Another method used to hit these corner cases is random test case generation. However, such random test cases can take millions of run cycles to achieve a single corner scenario.
What is needed, then, is a method for creating complex test scenarios that does not require excessive manual coding or the use of excessive random test cases.